By R. Joobbani
Routing of VLSI chips is a vital, time eating, and hard challenge. the trouble of the matter is attributed to the big variety of usually conflicting elements that have an effect on the routing caliber. conventional recommendations have approached routing by way of ignoring a few of these elements and implementing pointless constraints on the way to make routing tractable. as well as the imposition of those regulations, which simplify the issues to a point yet whilst decrease the routing caliber, conventional techniques use brute strength. they generally remodel the matter into mathematical or graph difficulties and fully forget about the explicit wisdom concerning the routing job which could vastly aid the answer. This thesis overcomes a number of the above difficulties and provides a process that plays routing just about what human designers do. In different phrases it seriously capitalizes at the wisdom of human services during this quarter, it doesn't impose pointless constraints, it considers all of the various factors that impact the routing caliber, and most significantly it permits consistent person interplay in the course of the routing approach. to accomplish the above, this thesis offers heritage approximately a few consultant ideas for routing and summarizes their features. It then reviews intimately the several elements (such as minimal region, variety of vias, twine size, etc.) that impact the routing caliber, and different standards (such as vertical/horizontal constraint graph, merging, minimum rectilinear Steiner tree, etc.) that may be used to optimize those factors.
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Additional info for An Artificial Intelligence Approach to VLSI Routing
N 3. Determine Ta(i) , Tb(i), Tab(i) from Ta(i-l), Tb(i-l), Tab (i-l). 1 belong to A. Case 1: Only ajis in A. a. L(Ta(i)) = L(Ta(i-l)) + d(i-l,i). ] to Ta(i-l). b. 1) depending on whether argument 1 one, two, or three is the minimum, respectively. c. L(Tb(i» = L (Tab(i)). The tree Tab(i) also serves as Tb(i). Case 2: Only b j is in A. This case is completely analogous to case 1. Case 3: Both aj and bj are in A. Here the tree Tab (i) and its cost are determined as in case 1(b). Moreover Ta(i) = Tb(i) = Tab(i).
Since routing, in this thesis and in general, is based on a rectilinear (Manhattan) grid, this section discusses rectilinear Steiner trees [Hwang 76, Hanan 66]. It has been proved that the general problem of constructing Minimal Rectilinear Steiner Tree (MRST) is an NP·complete problem [Even 79, Garey 77a, Garey 77b, Cockayne 70]. However there are some efficient special case algorithms [Aho 77, Hwang 78] for constructing MRST which are discussed in the next section. Also presented is an algorithm which uses geometric properties to reduce the number of possible alternatives for a mxn grid.
Figure 3-6 shows the case where the ordering of nets based only on wire length is misleading and does not always result in the best solution. In Figure 3-6(a) net 1 is routed closer to the bottom because it has 3 pins all on the bottom of the channel, more than any other net. Routing of net 1 in the first row pushes nets 2 and 3 to the second row. Figure 3-6(b) shows the same example routed with shorter wire length. In this example the designer has noticed that nets 2 and 3 can be routed (merged) on the same row and the effective pin count for both of these nets is 4 compared to 3 of net 1.